Off-Topic Discussion > Programming

Lets Learn Verilog!

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more than likely i will scrap them all for parts. i love questionable hardware. turn it into parts i will probibly never use.

Phantom Hoover:
i seek answers for the fundamental mystery of verilog:

what's the actual difference between it and vhdl

verilog looks like c, vhdl looks like ada. i havent looked at vhdl yet, im just going by what was on wikipedia/things i googled.

i did get my dac layed out, will etch as soon as i fill in the empty spaces with other unfinished projects. i didnt like the transfer paper i used before so im using that $2 a sheet blue press n peel stuff. at $2 a page im going to use the whole thing, even if i just end up printing a bunch of adapters and other prototyping stuffs. if i run out of things to do before my parts show up im just going to take the one channel prototype dac and try producing a b&w composite tv signal (no color since i dont have an ad725 laying around, unless i can synthesize one, i have some dsp slices to work with after all).

This thread immediately triggered college anxiety memories. Nobody is good at Verilog, nobody...I had to carry so many fail teams that every project felt like playing World of Tanks.


always @(negedge clock or negedge reset_b) begin
    if (!reset_b) begin crap = 1'b0; state = oh_my_gawd; end
    else case(state)
        oh_my_gawd: begin crap = 1'b1; if (enter) state = verilog_sux; else state = oh_my_gawd; end

9 years later and i still havent learned verilog.


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