finished the last tutorial, and i dont think i learned very much at all. all the tutorials pretty much did was cover stuff you would be better off with a micro controller to do. but i think i got enough of a handle on the hardware and verilog to do an actual project that i give a **** about.
ive attempted to design a video card from scratch before, using discrete logic components. my design was massive, i didnt have the right parts. the project never got very far beyond an oversized eagle schematic. the fpga lets me do things in a less masochistic way.
first order of buisness is a framebuffer. the fpga has about 512k of dual ported 9-bit (8+pairity bit) memory + an extra 90k of distributed memory. obviously the frame buffer will go in the 512k section. it will be a dual buffer so each frame needs to fit in 256k. my color depth will be 3'3'3 rgb, making use of the otherwise unused parity bit. now i cant quite get the vga standard of 640x480, i dont have the memory, the closest i can fit is 552x414, which will mean a border and not much room for anything else. if i drop down to 320x240, i can free up memory for other things like pallets and sprites. the abundance of pins however makes it possible for me to just stick a fast dram on an expansion board, but that will require me to build something, so il just use what i got.
video cards have more than just a frame buffer. if i want to do any kind of layering or 3d, i need a z buffer. i can still get 320x240 if i go with an 18-bit frame buffer giving me 9 for color and 9 for z. obviously 512 steps of z probibly wont look very good. i can borrow some bits from color in favor of z. if i use a 2'2'2 rgb color space, then i can have a 12 bit z buffer, or if i want more z, i can do 16 color pallets (in the 9'9'9 color space) with a 14 bit z buffer. if i dont eat up too much logic, i may even be able to do 27 bit frame buffer with 9'9'9 color and 18 bit z. so i have lots of options.
the pixel clock will probibly be pretty fast. i will need to use a counter and some comparators to generate sync pulses and another counter for the memory address, which will be counted up when i need the next pixel in sync with the pixel clock. i need to do the math to figure out what this will be. its dual ported ram, so all this stuff will be isolated from the part that does all the work. collisions shouldnt be an issue if i put each frame in different memory banks. i can render one and output the other.
to do a 3d card means i will need to have to do vector and matrix math on the fpga. fortunately it has 16 dsp slices on it which each have an 18 bit multiplier and a 48 bit accumulator. this should handle matrix multiply, dot products, vector transforms, lerp, etc quite nicely. probibly wont get things like lighting, or textured polygon fill, or shaders.
then there is communication. the board comes with a usb serial interface which i will use for initial testing. i can issue rendering commands over serial (all be it at a fairly slow rate), but eventually i will just do a synchronous parallel interface to speed things up. it will feed a fifo and commands will be handled as fast as possible.
obviously the first order of buisness is to output a usable vga signal. namely figuring out the frequency of the pixel clock, and all the timings.
anyway put a little effort into designing a resistive dac. unfortunately i dont have any female vga ports laying around, so i have to destroy a cable. the good news is i have spares. i can just use some strip board and some headers i got, and i have more resistors than i know what to do with. i considered using some buffers to boost 3.3v to 5v, and to isolate the fpga, but it turns out this is not neccisary. since the vsync/hsync signals can be 3.3v, and the resistors will be high enough to limit any feedback current. analog signals need to be 0-0.7v, and i may need to stick a divider on each ladder to bring the voltage down. will put it together tomorrow or whenever. probibly build one channel on a breadboard and test it with a multimeter to verify the design and make sure my values are correct. onve the hardware is out of the way it becomes a full on code project.