http://www.virtualdub.org/blog/pivot/entry.php?id=347It seems only Intel's compiler has support for multiple code paths allowing multiple SIMD instruction sets to co-exist within same executable. And even that only works on Intel CPU's. It would be daunting task for SCP to support more than two sets of executables, not to mention that simply switching instruction set from SSE2 to AVX often won't magically make the code faster. Sufficient manual code optimization would have to be done to fully utilize newer instruction sets, especially AVX. Otherwise you may actually see worse performance from AVX if you leave it to automatic optimization in the compiler.
This document may also be of interest:
http://www.agner.org/optimize/vectorclass.pdfAs FSO is still and will probably remain good while single-threaded for most parts, higher SIMD instruction set support would probably be nice to get more performance out of our new(er) CPU's. But each instruction set could use at least some degree of manual optimization for optimal performance, it's not quite as simple as just throwing /arch:SSE4 or /arch:AVX to the compiler and rely on automatic optimization. But this probably would create a support nightmare where bugs may be present in one arch but not another due to said manual optimizations that deviate from one arch to another.
I could probably see SCP ditching SSE2 support in favor of SSE3. SSE4 would be appealing but both Intel and AMD played it stupid by creating SSE4, SSE4a, SSE4.1 and SSE4.2 instruction sets and CPU support is spotty at best. I would suspect SSE4 to be support nightmare because of that. If SCP is willing to support three sets of executables, SSE, SSE3 and AVX would be good choices. But again, how much work does that really entail in the manual optimization front?
