Originally posted by HotSnoJ
This is how it was explained to me.
AMD pushes more data through per clock cycle, while Intel just pushes it through faster.
Well, firstly Hyperthreading is, IIRc, based on dual pipelining for parallel processing. i.e. you have to balance the loads on each pipeline to get a benefit, which is a bastard to do. the PS2 has a similar problem (it has 4 pipelines, I think)
Secondly, Intel have a habit of making very large pipelines with many stages. I believe it's 35 in the P4. Pipelining basically allows instruction execution to be divided into multiple clock cycles, so that the entire data poath is in use (i.e. while instruction 1 is using the ALU, instruction 2 can write the registers, etc).
Theoretically, this 'stepped' execution should allow one instruction to finish execution every clock cyle - hence giving the MHz rating. Theoretically, it should be much faster - i.e. a 4-stage pipeline is 4* faster than the same machine with no pielining (rough example).
Unfortunately, it doesn't work that way. Because instructions may be dependent on others, or use data that hasn't been written yet (by an incomplete instruction), 'Hazards' occur when inconsistencies develop. Hazards either require correction (which has a hardware overhead in terms of detection and fixing the hazard), or requiring the entire datapath (pipeline) be flushed and restarting.
Thus, pipelining has maximum effectiveness with about, IIRC, 8 stages. After 16 stages, performance actually begins to decline. eventually, the cost of hazards negates the benefit.
and the P4 pipeline is
35 stages long. Even with paralleleism and other such fancy stuff I don't know about, that's gotta be dodgy.
so why do it?
Simple, you can quote a higher MHz rating based on the theoretical maximum instruction throughput, and make your machine look better than it is. Hence why the ratio of actualimprovement to MHz difference is so misleading. Not to mention that the design gets hideously complicated and hard to manage through managing those hazards.
Now, I don;t know AMD's tactics. But, thanks to a ranting, intel hating yet very clever CAD (Comp Arch & Design) teacher, I know they're better at this design malarky.
