Actually, technically speaking the FSB speeds for the P4 family are 100, 133, and 200 MHz., but they are each expressed in terms of their effective performance of 4 times these figures, because they prefetch 4 bits per clock cycle instead of 1 or 2. Intel calls this its "quad pumped" technology, but its not the first to use something like it. AGP has 1x, 2x, 4x, 8x, and perhaps even 16x before switching to PCI-Express, each (with the exception of 1x) use this method to get more data in a single clock cycle, simulating a faster clock speed, even though it still operates on a 66 MHz. bus. Another example of this is with DDR-SDRAM, which grabs twice as much data in a single clock cycle, then re aligning the data back into a sequential form, so SDRAM of 100, 133, 166, and 200 MHz. can simulate speeds of 200, 266, 333, and 400 MHz. There are even DDR modules that can operate at 266, and thus simulate 533 MHz. The upcoming DDR2, could be refered to as QDR, since it uses sends 4 times as much data in a single clock cycle as standard SDRAM. Back on the FSB, and somewhat older, the system bus of AMD's Athlon CPU (not the AMD64 though) grabs 2 bits per clock cycle, which played a factor in the Athlon's gains over the Intel P3 until the P4 came into its own. I'm not sure what AMD's X86-64 designs use, since its architechture is somewhat different from normal.
In any case, a 1.8 GHz. cpu on a quad-pumped bus could either be a 18.0 clock multiplyer on a 100 MHz. system bus, 13.5 x 133.3 MHz, or 9.0 x 200 MHz.
Later!
